It is often the case that one or more integrated circuits are configured to divide a data stream into portions of data, and transmit the portions of data synchronously to a number of separate integrated circuits over a number of transmission lines. For example, a stream of N-bit input data may be split into eight equal portions and each N/8-bit portion synchronously transmitted to eight separate integrated circuits. Although eight has been used in this example, the concept applies to any number of divisions of data transmitted to any number of separate integrated circuits.
However, for a number of reasons (e.g., physical structure of transmission lines and/or operating conditions), the N/8-bit portions may be received by each separate integrated circuit out of synchronization with each other. For example, suppose an N-bit input data value X is provided by a transmitting integrated circuit at time t1. X is divided into N/8-bit data portions X1-X8 and synchronously transmitted to eight separate integrated circuits over eight transmission lines. However, because of the relative time delays between transmission lines, X1 may be received by a first receiving integrated circuit one or more clock cycles after X2 is received by a second separate receiving integrated circuit. As such, X1 and X2 are out of synchronization. Because X1 and X2 are out of synchronization, X1-X8 cannot be concatenated to reproduce X at an output node coupled to each of the separate receiving integrated circuits.